The present invention relates generally to boost circuits for use in low-power memory devices, and more particularly, to a protection circuit that allows a high-speed transistor to be used in a boost circuit for a low-power memory device.
For low voltage operation of a memory device, for example a xe2x80x9cFlashxe2x80x9d memory device, a word line voltage-boosting scheme is used to boost the voltage levels of word line signals used to operate the memory. However, typical boosting circuits may damage or stress high-speed memory components (i.e., transistors) and require the use of more robust memory components that operate at lower speeds.
FIG. 1 shows a typical boosting circuit 100 for use in a flash memory device. Transistor (Q1) is a depletion N-channel transistor that has a negative voltage threshold (Vt) approximately equal to xe2x88x921.0 volts. As a result, the voltage at node Nb is set to Vcc when a boost activation input signal (Kickb) is at a high level. The Kickb signal being a signal used to operate the memory device during burst mode when signal boosting is required.
The node Nb is connected to Xdecoder circuits that select one of multiple word lines according to an address input. The Xdecoder circuits and word lines also act as loading capacitance for the booster circuit output. When the Kickb signal transitions from a high to low level, the voltage on node Nb is boosted and becomes:
Vnb=Vcc+(Cb/(Cb+Cl))*Vccxe2x80x83xe2x80x83(1)
The Xdecoder applies the boosted voltage to a selected word line. From the above equation, it can be seen that the boosted voltage cannot be higher than 2*Vcc. However, the boosted voltage is required to go higher for super low Vcc operation, for example, when Vcc is approximately equal to 1.8 volts. In this case a multi-stage booster is used.
FIG. 2 shows a typical two-stage boost circuit 200 that can generate a boosted voltage higher than 2*Vcc. When the Kickb signal is at a high level xe2x80x9cHxe2x80x9d, then Nb and Nb2 voltages are set to Vcc through transistors Q2 and Q1. When the Kickb signal goes to a low level xe2x80x9cLxe2x80x9d, the node Nb voltage is boosted in the same manner as specified in the equation (1) above. Some time later, the second stage booster boosts the node Nb2 voltage to a level that is higher than Vcc according to the expression:
Vnb=Vcc+(Cb/(Cb+Cl))*Vnb2
where
Vnb2=Vcc+(Cb2/(Cb2+Cl2))*Vcc
and
Cl2=(Cb1*Cl)/(Cb1+Cl)
Thus, from the above equations the voltage at Nb2 could be as much as 2*Vcc, so that just less than 3*Vcc is also possible on the node Nb.
Unfortunately these high voltage levels may cause damage to the circuit components. For example, the booster circuit is required to operate at high speed. In order to have fast boosting speed, a high-speed transistor should be used for transistor Q3. However, a high speed transistor for Q3 has thin gate oxide. When the node Nb2 is boosted higher than Vcc, the transistor Q3 may have excess voltage stress across its gate oxide (i.e. its drain to gate voltage may exceed specified limits), which may cause the gate oxide to break down and Q3 to fail. Simply replacing Q3 with a transistor having a thicker gate oxide creates another problem, since such a transistor operates at a slower speed and would negatively impact the speed of the booster circuit.
Therefore is would be desirable to have a booster circuit that maintains high operating speed without risking transistor failure due to oxide breakdown occurring as a result of the boosted voltage levels.
The present invention includes a protection system that provides protection for a booster circuit used in memory devices to boost operating signals of the device. The protection system allows operating signals to be boosted without causing component failures due to the effect of the boosted voltages.
In one embodiment of the invention, the protection system adjusts the voltage on a gate terminal of a high-speed transistor used in a boost circuit. The adjusted gate voltage reduces stress on the gate oxide (i.e. by adding voltage to the gate terminal) and thereby averts gate failure of the high speed transistor. In another embodiment of the invention, the protection system capacitively couples a selected capacitance to a gate terminal of a high-speed transistor used in a booster circuit. As a result, the gate voltage is adjusted to reduce the gate oxide stress and avert gate failure of the high-speed transistor.
In one embodiment of the invention, a protection circuit is provided for protecting an output transistor of a boost circuit that boosts the voltage level of a memory signal used to operate a memory device. The protection circuit includes a transfer gate coupled to the output transistor and coupled to receive a first boost signal and a second boost signal. The transfer gate is operable to open and close in response to the second boost signal. When the transfer gate is closed the first boost signal is uncoupled from the output transistor, and when the transfer gate is opened the first boost signal is coupled to the output transistor. The protection circuit also includes a protection transistor coupled to the second boost signal, a supply voltage and the output transistor. When the transfer gate is opened in response to the second boost signal, the protection transistor operates to couple the supply voltage to the output transistor.
In one embodiment of the invention, a protection circuit is provided for protecting an output transistor of a boost circuit that boosts the voltage level of a memory signal used to operate a memory device. The output transistor has a channel capacitance between its gate and source terminals. The protection circuit includes a transfer gate coupled to receive a first boost signal and a second boost signal. The transfer gate is operable to open and close based on the second boost signal, wherein when the transfer gate is open the first boost signal is coupled to the gate terminal of the output transistor, and wherein when the transfer gate is closed the first boost signal is uncoupled from the gate terminal of the output transistor. When the first boost signal is uncoupled from the gate terminal, a voltage level on the gate terminal increases due to the channel capacitance. The protection circuit further includes an inverter coupled to the second boost signal and the transfer gate.
In one embodiment of the invention, a method is provided for protecting an output transistor of a boost circuit that boosts the voltage level of a memory signal used to operate a memory device. The method includes steps of receiving first and second boost signals, gating the first boost signal, wherein the first boost signal is selectively coupled and uncoupled to the output transistor in response to the second boost signal, and adding voltage to a gate terminal of the output transistor when the first boost signal is uncoupled from the output transistor.